A present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device which is electrically flasherasable.
An EEPROM flush memory which is inexpensive and flasherasable has been well known as one kind of EEPROMs. Many flash memories have been developed, and one of them is disclosed in "IEDM 91 Technical Digest", 11. 5. 1 (p311 to p314).
The structure of such conventional EEPROM flash memory will be described using FIGS. 10-14. FIGS. 11-14 are sectional views of a memory cell section taken along the line A-A' of FIG.10.
First, as shown in FIG. 11, a first silicon oxide film 14, a first polycrystalline silicon film 15 and an ONO film 18 are sequentially formed on a P type silicon substrate 11.
Next, as shown in FIG.12, the ONO film 18 and the first polycrystalline film 15 are sequentially removed in a stripe shape and the remaining films 18 and 15 extend in a column direction.
Subsequently, as shown in FIG. 13, arsenic ions are implanted into the P type silicon substrate 11 using the first polycrystalline silicon films 15 and the ONO films 18 as masks, whereby N type diffusion layers constituting buried diffusion layers 16 serving as bit lines are formed. Next, a second silicon oxide film 13 is formed by a CVD method, the second film oxide film 13 has such a thickness that intervals between the first polycrystalline silicon films 15 are completely buried. Subsequently, an anisotropic etching is performed for removing the quantity of a thickness equivalent to that of the second silicon oxide film 13, thereby obtaining the structure shown in FIG.13.
Next, as shown in FIG. 14, a second polycrystalline silicon film 17 serving as a control gate of the memory cell is formed. After a lithography step, the second polycrystalline silicon film 17 is etched to stripe, specifically, separate pieces of the film 17 form the stripe in the row direction. Moreover, the ONO film 18 and the first polycrystalline silicon film 15 are sequentially etched, whereby the conventional EEPROM flash memory is completed.
However, in the conventional EEPROM flash memory, as micronization of the memory cell is advanced, a width of the channel region is narrowed so that a desired ON current of the memory cell will not able to be secured. Particularly, when the conventional EEPROM flash memory is applied to a multi-value memory in which more than four values (00, 01, 10, 11) is stored in each memory cell, large ON current of the memory cell of such memory than that of a two-value (0, 1) memory is required. For this reason, there has been a problem that it will be more difficult to realize a memory cell of much values as the micronization thereof advances.
Furthermore, since a height of the memory cell region is taller than those that of peripheral region in which a decoder circuit, a buffer circuit and the like are formed, the step difference between the memory cell region and the peripheral region are large, so that problems in the fabricating process such as photo lithography process arise.
Furthermore, as disclosed in Japanese Patent Application Laid Open No. hei 7-45797, there has been a way in which a groove is formed on a semiconductor substrate and a channel of a memory cell is formed on the side surface of the groove.
However, in the art disclosed in the Japanese Patent Application Laid Open No. hei 7-45797, although a degree of integration is advanced because the side surface of the groove is used as the channel of the memory cell transistor, it has been difficult to increase the ON current.